1. Field of the Invention:
The present invention relates to a semiconductor memory device and a manufacturing method thereof. More particularly, the present invention relates to a semiconductor memory device including a plurality of memory cells, each having a switching transistor and a capacitor connected thereto and a manufacturing method thereof.
2. Description of the Prior Art:
For reducing the size of a memory cell of a semiconductor memory device, a construction in which an electrode (storage node) of a capacitor is formed in a trench has been proposed. For example, a stacked trench semiconductor memory cell is disclosed in Technical Digest of 1987 IEDM, pp. 332-335.
A manufacturing method of a conventional stacked trench DRAM will be described with reference to FIGS. 9A through 9J. FIGS. 9A through 9E illustrate a cross section of a memory cell in each manufacturing step of the conventional stacked trench DRAM. FIGS. 9F through 9J illustrate a cross section of a plate potential applying section disposed in a peripheral region of a memory cell array in each manufacturing step. FIGS. 9A through 9E and FIGS. 9F through 9J respectively show the same steps.
As is shown in FIGS. 9A and 9F, a trench is formed in a portion of an active region of a semiconductor substrate 114 which has an oxide film 11 and a nitride film 10 on a surface thereof, and then, an oxide film sheath 13 is selectively formed on an inner wall of the trench. As is shown in FIG. 9B, a portion of the trench which is located in the memory cell is covered with a resist 3. The oxide film sheath 13 in a portion of the trench which is located in a peripheral region of the memory cell array and thus is not covered with the resist 3 is removed as is shown in FIG. 9G, thereby exposing a portion of the semiconductor substrate 114. Then, an n-type impurity is diffused over the exposed portion of the semiconductor substrate 114, thereby forming an n-type impurity diffusion layer 7 in the semiconductor substrate 114 as is shown in FIGS. 9C and 9H.
After a polysilicon film 4 is formed on the inner wall of the trench, a capacitive oxide film 5 is formed on the polysilicon film 4, and the trench is filled with a resist 6. Portions of the capacitive oxide film 5, the polysilicon film 4 and the resist 6 which are located outside the trench are etched away. In this way, the capacitive oxide film 5, the polysilicon film 4 and the resist 6 are left only in the trench as is shown in FIGS. 9C and 9H.
Then, another polysilicon film 8 is formed so as to fill the trench. A portion of the polysilicon film 8 which is located outside the trench is removed using an etchback technique, thereby leaving the polysilicon film 8 only on the capacitive oxide film 5 as is shown in FIGS. 9D and 9I. Then, a lithography technique is used to form a resist 9 having openings at specified positions and then to etch away a portion of the oxide film sheath 13 which is located on a contact area of the inner wall of the trench. In this way, a side wall window is formed in the oxide film sheath 13. As is shown in FIG. 9I, the trench located in a peripheral region of the memory cell array is covered with the resist 9.
The polysilicon film 8 located in the trench of the memory cell functions as a storage node 81, while the polysilicon film 8 located in the trench of the plate potential applying section functions as a plate potential applying electrode 82.
After the nitride film 10 is removed, still another polysilicon film is deposited on the entire surface of the semiconductor substrate 114. The polysilicon film deposited on the semiconductor substrate 114 is thermally oxidized, thereby forming an oxide film 12 on the storage node 81 and the plate potential applying electrode 82. Then, the oxide film 11 is removed from an active region, thereby forming a source and a drain (not shown) of a transistor in the active region. The source is electrically connected to the storage node 81 through the side wall window.
The n-type impurity diffusion layer 7 of the plate potential applying section in the peripheral region of the memory cell array is connected to the n-type impurity diffusion layer 7 of the memory cell, and the n-type impurity diffusion layer 7 is in direct contact with the plate potential applying electrode 82. Accordingly, the plate potential is supplied from the plate potential applying electrode 82 to the polysilicon film 4 of the memory cell, the polysilicon film 4 functioning as a plate electrode. Therefore, when a voltage is generated between the polysilicon film 4 functioning as a cell plate and the storage node 81, the capacitive oxide film 5 has a charge stored on both side surfaces thereof.
In such a conventional stacked trench semiconductor memory device, further reduction of the size thereof accompanying the improvement of the memory capacity results in difficulty in the alignment which is conducted by the use of the lithography technique for forming the side wall window (FIG. 9D). Inferior alignment will significantly reduce the production yield. Moreover, the contact resistance is increased due to a native oxide film existing on the side wall contact.